A Compositional Rule for Hardware Design Refinement

We present an approach to designing veriied digital systems by a sequence of small local reenements. Reenements in this approach are not limited to a library of predeened transformations for which theorems have been previously established. Rather, the approach relies on localizing the reenement steps in such a way that they can be veriied eeciently by model checking. Toward this end, a compositional rule is proposed by which each design reenement may be veriied independently, in an abstract environment. This rule supports the use of downward reenement maps, which translate abstract behavior detailed behavior. These maps may involve temporal transformations, including delay. The approach is supported by a veriication tool based on symbolic model checking.